Freescale Semiconductor /MKE04Z1284 /SIM /CLKDIV

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CLKDIV

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)OUTDIV3 0 (0)OUTDIV2 0 (00)OUTDIV1

OUTDIV1=00, OUTDIV2=0, OUTDIV3=0

Description

Clock Divider Register

Fields

OUTDIV3

Clock 3 output divider value

0 (0): Same as ICSOUTCLK.

1 (1): ICSOUTCLK divides by 2.

OUTDIV2

Clock 2 output divider value

0 (0): Not divided from divider1.

1 (1): Divide by 2 from divider1.

OUTDIV1

Clock 1 output divider value

0 (00): Same as ICSOUTCLK.

1 (01): ICSOUTCLK divides by 2.

2 (10): ICSOUTCLK divides by 3.

3 (11): ICSOUTCLK divides by 4.

Links

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